1. Technical Field
The present disclosure relates to a semiconductor device, and more particularly, to a cache memory device capable of improving the performance of writing/reading data between a host and a non-volatile memory device, and a data processing method of the cache memory device.
2. Discussion of Related Art
Data transmission speed of a host in a system including a Serial Advanced Technology Attachment (SATA) oriented Solid State Disk (SSD) may be higher than in systems that make use of other memory devices, such as a NAND type Electrically Erasable and Programmable Read Only Memory (EEPROM) based non-volatile memory device. Accordingly, a system including the SATA oriented SSD may require a large-capacity buffer for smooth data transmission.
FIG. 1 is a block diagram of a conventional non-volatile memory system that includes a buffer. Referring to FIG. 1, the non-volatile memory system 10 includes a host 20, a buffer 30, and a non-volatile memory device 40.
The buffer 30 in the non-volatile memory system 10 has a large capacity for storing data transmitted from the host 20 to the non-volatile memory device 40, because the data processing speed of the host 20 is much faster than that of the non-volatile memory device 40. The buffer 30 temporarily stores data that is received from the host 20 and data from the non-volatile memory device 40 that is destined for the host 20. The buffer 30 may be embodied as a volatile memory device such as a Synchronous Dynamic Random Access Memory (SDRAM).
The non-volatile memory device 40 receives and stores data output from the buffer 30. The non-volatile memory device 40 includes a memory cell array 41 having non-volatile memory cells such as a NAND type EEPROM, and a page buffer 43. The memory cell array 41 exchanges data with the buffer 30 through the page buffer 43. The non-volatile memory 10 is less efficient because the buffer 30 is only used for buffering data transmitted to the non-volatile memory device 40.
The page buffer 43 reads or writes data in the units of a page. Each page may include n sectors, where n is a natural number and equals 8. For example, when there are four channels between the buffer 30 and the non-volatile memory device 40 and data is transmitted from the buffer 30 to the non-volatile memory device 40 across the channels, pages having 32-sectors(=4*8-sector) may be required for the non-volatile memory system 10 to operate optimally.
However, when the size of data transmitted from the buffer 30 to the non-volatile memory device 40 is less than 32-sectors, the non-volatile memory system 10 becomes less efficient since some of the four channels may not be used.
Thus, there is a need for a cache memory device capable of improving performance of writing/reading data between a host and a non-volatile memory device, a method of operating the cache memory device, and a system that includes the cache memory device.